UML-Based Rapid Prototyping Design Flow for Dynamically Reconfigurable Computing Systems

Dynamically reconfigurable computing systems (DRCS) provides an intermediate tradeoff between flexibility and performance of computing systems design. Unfortunately, designing DRCS have a high complexity and is a formidable task. Although many researches are ongoing in the academia and industry, but the lack of tools and design flows discourage designers from adopting the reconfigurable computing technology. A UML-based design flow for DRCS is proposed in this Thesis. The proposed design flow is targeted at the execution speedup of functional algorithms in DRCS and at the reduction of the complexity and time-consuming efforts in designing DRCS. In particular, the most notable feature of the proposed design flow is a HW-SW partitioning methodology based on the UML 2.0 sequence diagram, called Dynamic Bitstream Partitioning on Sequence Diagram (DBPSD). Besides, partitioning guidelines are also included in DBPSD to help designers make prudent partitioning decisions at the class method granularity. The enhanced sequence diagram in UML 2.0 is capable of modelling complex control flows, thus the partitioning can be done efficiently on the sequence diagrams. To prove the feasibility of the proposed design flow and DBPSD partitioning methodology, an implementation example of DES (Data Encryption Standard) encryption/decryption system is presented in this Thesis. It was found from the implementation result that different control flows affect the number of times each method is invoked in an application. Thus, the worth of doing partitioning on sequence diagram according to control flow is proved.